The complete schematic for Prototype IV can be found here. This is the electrical expression of the ideas outlined in my previous post. For the most part, nothing has changed. Use the first page of the schematic (Block Diagram) to get an overview of how the features have been included in the design.

1. Block Diagram. Notice that ATA is about the only pin group not used in the design.
2. Boot Configuration. We are using the default boot configuration. Could be changed via jumpers.
3. Core Logic. Memory and I/O signals of the MPC5200. Here is a list of the pin group assignments:
   1. PSC1: Configured as a Codec in Cell Phone mode. The clock pulse from the MAX9585 is input on the BitClock of this port. This port acts as the Cell Phone master for PSC2.
   2. PSC2: Configured as a Codec in Cell Phone mode. This PSC is a Cell Phone slave to PSC1. It is the source of the I2S stream to the TAS5504.
   3. PSC3: Configured as USB. The USB pin group was configured as two UARTs so the USB function was moved to this pin group.
   4. USB: Configured as UART4 & 5. The design needs a serial port for Boot (UART4) and Insteon (UART5). The USB pin group is the only pin group that can have two UARTs. So USB was moved to the PSC3 pin group.
   5. Ethernet: Configured as Ethernet. This pin group connects to the Power Line modem.
   6. PSC6: Configured as SPI. This pin group connects to the SD Card connector. SD Cards are going to be used for our mass storage.
   7. Timers: Configured as GPIO. This pin group connects to the various control lines for the peripherals. There is a note on the schematic with the assigned functions.
   8. IRQs: The CPU can be interrupted by PCI or the amplifier power stages (on over heat or shutdown).
   9. I2Cs: I2C1 is connected to the TAS5504. I2C2 is connected to the MAS9485. Jon says the TAS5504 requires a lot of configuration information so he wants to run the I2C lines at full speed. So I2C1 will be high speed and I2C2 will be left for slow speed devices.
   10. Dedicated GPIO: The CPU can be woke-up on IR signal or by the PCI bus. I think we still need to find a way to wake-up the CPU on Insteon and Power Line events. Hmm...
   11. LocalBus: Contains two 16MB Flashes. One is on CS0 and the other is on CS1. There are jumpers so they can be swapped.
   12. MemoryBus: Configured for DDR. There is 64MBs of 133MHz RAM.
4. Core Clocks & Debug. The MPC5200 JTAG interface has been brought out. We plan on purchasing a JTAG probe for boundary scan and programming the Flash. Notice that we are using two voltage monitors (MAX6717 - open collectors) to hold the CPU in reset until all the power rails are stable.
5. Core Power. Bunch of capacitors to provide immediate power to the CPU.
6. Flash Memory. We have included 32MBs of memory in two Flash chips. They are on separate chip selects that can be swapped. The idea here is that one can be used as backup during development.
7. Insteon Interface. DigiSpeaker can be commanded with Insteon devices through this interface. It connects to the CPU via UART5. It detects/transmits 131.65KHz signals on the powerline.
8. Ethernet via PCI. The Ethernet interface on the MPC5200 is used by the Power Line modem so regular ethernet has been added via PCI.
9. Power Line Modem Controller. This is the Power Line modem controller and Analog Frontend from Intellon.
10. Power Line Modem Driver. More Power Line modem stuff. This is the actual interface to the powerline. It transmits packets simultaneously on several channels between 4MHz and 22MHz (transmit path). It can receive them as well (receive path).
11. Pulse Width Modulator. All four outputs of the PWM have been connected to output stages. This schematic also has the clock chip that drive the Cell Phone mode PSCs.
12. Primary Output Power Stage. Channels 1 & 2 of the TAS5504 are connected to this power stage. The two channels are configured as BTL.
13. Secondary Output Power Stage. Optional second power stage. Channels 3 & 4 of the TAS5504 are connected to this power stage. There are jumpers to configure the power stage as PBTL. In which case, channel 4 of the TAS5504 is used. Otherwise, it can be configured as two BTL channels.
14. Memory Bus Terminators. Inline current limiters for the SDRAM memory lines.
15. SDRAM. 64MBs of 133MHz SDRAM.
16. Serial Port, SDIO & IR Remote. Boot serial port that can be used to monitor the system. SD Card connector that is used as mass storage. IR receiver so DigiSpeaker can be commanded with an IR remote.
17. USB. USB connector for whatever device we think we need. Ideas are Z-wave or Wifi.
18. Power Regulation. This prototype is designed to work with a three rail power supply (24V, 12V & 5V). The remaining power rails are created with LDOs.